The dynamic random access memory (hereinafter, referred to as DRAM) which is one example of the semiconductor memory device is mounted in various types of electronic equipment used in our daily life, for example, in a main memory of a large-scale computer and a personal computer and a work memory of digital electronics such as a cellular phone and a digital camera. In addition, with the increasing needs for the lower power consumption and higher performance in the equipment in recent years, the high-performance DRAM capable of achieving the low power consumption, the high-speed operation, and the large capacity has been strongly demanded.
The most effective method to realize the high-performance DRAM is to scale down the cell transistors and the cell capacitors used in a memory cell of the DRAM. The scaling down of the cell transistors and the cell capacitors makes it possible to reduce the size of the memory cell. As a result, the length of the gate line is reduced and the parasitic capacitance of the data line can be reduced. Consequently, the low voltage operation is enabled and the low power consumption can be achieved. Also, since the parasitic capacitance of the data line can be reduced, the sense amplifier can be operated at high speed. Furthermore, the merit obtained from the scaling down is significant, for example, the improvement of the performance of the equipment resulting from the increase of the capacity of the memory. Therefore, the performance of not only the existing products but also the products under development can be improved by the scaling down.
However, due to the further scaling down in the 0.1 um node or the 0.065 um node and 0.045 um node like in the existing product, various side effects occur in addition to the above-described effects of the performance improvement. The side effect includes the malfunction caused when reading a signal of the memory cell due to the variation in device characteristics which is increased by the scaling down. In this case, the variation in device characteristics means, for example, the difference in intensity of the threshold voltage of the cell transistor and the leakage current from the cell transistor (deviation from the average value). As described above, if the variation in device characteristics is large, various problems occur. For example, the data retention characteristics of the DRAM are degraded, and the yield of the chip is reduced. In particular, it is concerned that the variation in threshold voltage of the sense amplifier circuit increases in the future. This is because the data line pitch of the memory cell is very narrow in the recent DRAM and thus the size of the sense amplifier circuit connected to the data line must be reduced in the layout. Therefore, the processing error of the transistors constituting the sense amplifier becomes large, and as a result, the variation in threshold voltage of the pair transistor is increased. Usually, this problem is called the offset of the sense amplifier, and causes a large influence on the performance of the DRAM. In addition, the problem of the offset of the sense amplifier is described in detail in “VLSI Memory Chip Design”, pp. 195 to 247, Springer, 2001 by Kiyoo Itoh, and it is well known that the reduction of the offset greatly contributes to the improvement of the yield of the DRAM. Therefore, for the achievement of the performance improvement by the scaling down, the circuit design which can achieve not only the reduction of the processing error but also the reduction of the sense amplifier offset is required as an important technology in the future.
As an example for the solution of the above-described problems, ISSCC2002 Dig. Tech. Papers, pp. 154 to 155 by Sang Hoon Hong et al. discloses the technology for canceling the sense amplifier offset. In this method, the precharge voltage of the data line is corrected by using a current mirror operational amplifier. By doing so, the offset of the sense amplifier can be substantially reduced. However, since the number of devices added to the sense amplifier is vary large and the area of the sense amplifier is increased in this method, the chip size is increased. In addition, since the control signals to be driven are also increased, the timing margin is increased, and thus, the reduction of the operation speed is concerned. Also, “2003 symposium on VLSI Circuits Dig. Tech. Papers, pp. 289 to 292” by Jae-Yoon Simm et al. discloses a charge-transfer type sense amplifier. In this method, the charge accumulated in a peripheral circuit such as a sense amplifier is transferred to a data line on the memory cell side via a switch transistor connected to the data line so as to generate large potential difference in the sense amplifier. Therefore, even when the offset of the sense amplifier is increased, since the potential difference larger than the offset can be applied to the sense amplifier, it stands up well to the variation and is superior in the low-voltage operation. However, also in this method, since a number of additional devices, for example, a precharge circuit and a switch transistor for rewriting are required, the chip size is increased.